可以帮我解释一下吗?上次没复制好,谢谢了fenx
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fenx is
port
(clk:in std_logic;
qout:out std_logic
);
end fenx;
architecture behave of fenx is
constant counter_len:integer:=1999999;
begin
process(clk)
variable cnt:integer range 0 to counter_len;
begin
if clk'event and clk='1' then
if cnt=counter_len then
cnt:=0;
else
cnt:=cnt+1;
end if;
case cnt is
when 0 to counter_len/2=>qout<='0';
when others =>qout<='1';
end case;
end if;
end process;
end behave;