讲解一下程序
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity duAD is
port (
fosc : in std_logic;
adwr : out std_logic;
addatain: in std_logic_vector(7 downto 0);
addataout : out std_logic_vector(7 downto 0);
oe: out std_logic;
glbrst : out std_logic;
AD_addr: out std_logic_vector(3 downto 0);
JSTART: in std_logic;
fifo1_wr : out std_logic;
adcs: out std_logic;
adrd: out std_logic;
adgen : out std_logic;
convst : out std_logic;
adwb: out std_logic;
fifo1datain : out std_logic_vector(7 downto 0)
);
end duAD;
architecture Behavioral of duAD is
signal AD_cnt : integer range 0 to 127:=0; -- 时钟分频
signal fifo1_wr1 : std_logic;
signal adgen1 : std_logic;
signal rst : std_logic;
signal number : integer range 0 to 2000:=0;
signal AD_ch : std_logic_vector(3 downto 0);
signal ADdatain1 : std_logic_vector(7 downto 0);
begin
process(fosc)
begin
if fosc 'event and fosc= '1' then
if number=999then
number<=number;
rst<='1';
else
number<=number+1;
rst<='0'; ----低电平复位
end if;
end if;
end process;
glbrst<=rst;
fifo1_wr<=fifo1_wr1;
AD_addr<=AD_ch;
process(fosc,JSTART,rst)
begin
if rst='0'then
AD_cnt<=0;
elsif fosc 'event and fosc= '1' then
if JSTART='0'then
if AD_cnt=127 then
AD_cnt<=0;
else
AD_cnt<=AD_cnt+1; --计数,
end if;
end if;
end if;
end process ;
process(fosc,JSTART,rst)
begin
if rst='0'then
adgen1<='0';
elsif fosc 'event and fosc= '1' then
if JSTART='0'then
adgen1<='1';
else
adgen1<='0';
end if;
end if;
adgen<=adgen1;
end process ;
process(fosc,JSTART,rst)
begin
if fosc 'event and fosc= '1' then
if rst='0'then
AD_ch<="0000";
fifo1_wr1<='1';
casenumber is
when 50=>
convst<='1';
adwb<='1';
adcs<='0';
adwr<='0';
adrd<='1';
oe<='0';
when 51=>
addataout<="00010000";
when 52=>
adwr<='1';
when 53=>
adcs<='1';
oe<='1';
when others=>
end case;
elsif rst='1' then
if JSTART='0'then
caseAD_cnt is
when 2=>
convst<='1';
adwb<='1';
adcs<='0';
adwr<='0';
adrd<='1';
oe<='0';
when 3=>
addataout<="00010000";
when 4=> ---3----
adwr<='1';
when 5=> ---4----
adcs<='1';
convst<='0';
oe<='1';
when 19=>
convst<='1';
adcs<='0';
adrd<='0';
when 30=>
ADdatain1<=ADdatain;
when 45=>
fifo1_wr1<='0';
fifo1datain<="0000"&AD_ch;
when 46=>
fifo1_wr1<='1';
when 74=>
when 79=>
fifo1_wr1<='0';
fifo1datain<=ADdatain1;
AD_ch<=AD_ch+1;
when 80=>
fifo1_wr1<='1';
when others=>
end case;
end if;
end if;
end if;
end process ;
--<=ADdata_reg;
end Behavioral;